The present invention relates generally to semiconductor devices. More particularly, the invention relates to highly resistive interconnects (electrical connections between conductors in different layers of a semiconductor device), methods of making such highly resistive interconnects together with low resistive interconnects, and SRAM cells incorporating such highly resistive interconnects.
The background material and description of the present invention make primary reference to "contacts," that is, interlayer electrical connections between a region of doped silicon (such as a MOS transistor source/drain region) and a metal region. However, the present invention is equally applicable to interlayer electrical connections between two metal regions in a semiconductor device, commonly known as "vias." Where the invention is described with reference to contacts below, it should be understood that the principles are equally applicable to vias where a metal-to-metal interconnects are used, so that the invention is applicable to interconnects generally.
SRAM cells are typically used for data storage in memory and logic devices. These cells act as cross-coupled latches, with one node physically storing a logic level zero, while the second level physically stores a logic level 1. The connections to a power supply and ground maintain the logic levels at the power supply voltages, charging or discharging any small disturbance charge level. Zero standby power dissipation can be achieved with SRAM cells that are build with CMOS transistors. These tend to occupy a large area of silicon (Si), and are not used for high density memory. Instead, resistive load NMOS cross-couple latches are used to reduce silicon area and achieve high cell density.
A diagram of such a cross-couple latch is shown in FIG. 1A. The circuitry for writing data into the latch is not shown. The latch 100 is designed such that one NMOS transistor is off (say N1). That will force the node Vout2 102 to Vcc, and force N2 to be on. Load resistor (Rload) 104b and transistor N2 are ratioed such that when N2 is on, Vout1 is close to Vss. Vout1 106 is forced on the gate of N1, maintaining N1 in its off state. Thus, there is a feedback loop that is consistent in a cross-couple latch that will maintain Vout1 106 near Vss, and Vout2 102 at Vcc as long as the power supplies are activated.
This technique allows for some DC power dissipation, or non zero standby power usage. As one of the transistors in the cross-couple latch is always on, say N2 in this example, there is a current path from Vcc 108 to Vss 110 via Rload 104b and N2. Rload 104b is designed to have a very high resistance to limit this current flow. As every memory cell has one such current path, the total power dissipation is critical for high density memory devices. In order to keep the current level low in a SRAM cell, the load resistance is typically controlled at about 100 KOhm (.OMEGA.)-10 G.OMEGA., more typically 100 K.OMEGA. to 1 G.OMEGA..
Conventionally, this high resistance is obtained by using a second, very lightly doped (resistor--lower doping achieves a high resistance) polysilicon (poly) layer. FIG. 1B illustrates such a conventional implementation for a portion of a SRAM cell. A V.sub.CC bus 152 is connected to a transistor drain 154 by a pair of contacts 156 and 158 linked by a resistor poly layer 160. The transistor 162 also includes a poly gate 164 with a gate electrode 166 and a source 168 which is connected to V.sub.SS 170. The resistor poly layer 160 is not co-extensive with the gate poly 164 of the transistor 162, and the contact 158 is typically formed by a complicated "buried" contact process.
The doping on the resistor poly layer 160, which determines the resistance, is not well controlled, and typically leads to large variations in the resistor value. A polysilicon layer has grain boundaries, and the dopant diffuses at different rates through the grains and the grain boundaries. This makes doping of polysilicon imprecise. Hence the resistance value exhibits large variations within adjacent sites on the same die. The resistor poly layer is deposited after the transistor's poly gate electrode layer is deposited. It also has different doping compared to the gate electrode poly layer. The poly load resistor occupies horizontal space in the cell layout, adding to the cell size area of a memory cell. The most common technique to integrate a poly load resistor is by formation of a "buried" contact, noted above. This technique allows a poly resistor to directly contact the Si substrate at the expense of more complicated processing requirements. Thus, this conventional process for generating high resistance requires two levels of poly and involves imprecise doping techniques, and the layout must include a feature (resistor poly) that takes up additional area on the chip.
There are also schemes discussed in the literature, where different concepts are presented in order to reduce SRAM cell size. Some of these techniques use vertically integrated resistor techniques to use up less area. For example, vertically integrated resistors may have poly deposited into vertical vias. The resistance of the poly may be controlled according to different methods. According to a first method, a high resistance contact is obtained by doping the poly with oxygen or nitrogen implantation. Another method of forming high resistance contacts is by not doping the poly at all. While these techniques succeed in reducing cell area, the via fill poly adds process complexity, while the doping and implant techniques add a large degree of variation to the resistor value, as noted above.
Also, high resistance contacts formed by self-aligned silicide processes are known. In one such process, the resistance of a contact is determined by the formation of a metal silicide (or salicide) at the contact/silicon substrate interface. The presence and amount of metal silicide formed reduces the resistance of the contact relative to a contact formed entirely of unaltered metal. Alternatively, metal may be prevented from forming a metal silicide by first converting it to metal nitride by selective Nitrogen implant. However, these high resistances are typically &lt;1-10 K.OMEGA. range, and do not offer the high magnitudes needed for SRAM cells. Furthermore, these silicidation processes are applicable only to contacts since the via's metal-to-metal connection provides no silicon for silicide formation. Further, the process of forming contacts in this way is difficult to precisely control and may result in variability in the resistance value of the contacts obtained by nominally the same processing.
In addition, SRAM cells having side-by-side high and low resistance polysilicon contacts are known. The resistance of the contacts is controlled by doping, with higher resistance contacts being undoped and lower resistance contacts being doped with an ion to decrease resistance. As previously noted, doping or implanting of interconnects to define resistance has the drawback that dopant diffuses at different rates through the grains and the grain boundaries of polysilicon. Thus, the there may be large variations in resistance within adjacent sites on the same die.
Thus, it would be beneficial to be able to form high resistance value interconnects (contacts and/or vias) that can be vertically integrated into fabrication process so that cell size may be minimized and the use a second poly layer and of buried contacts are avoided, while also allowing for precise control of resistance value with relative simple and few process steps. Such a technique would greatly enhance the ability to make high density memory devices at low cost.